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SoC Physical Design Engineer

A successful candidate will be responsible for aspects of physical design implementation from RTL Synthesis to GDS with key responsibilities include:

  • Interacting with RTL and DFT counterpart to develop timing constraints and resolve design issues for timing closure
  • Static timing analysis, timing closure and signal integrity
  • Power grid analysis
  • Physical Design Verification (DRC, MRC and LVS)
  • Power analysis
  • Synthesis, floorplan, place & route
  • Physical Design methodology enhancements

  • BS or MS degree in Computer and/or Electrical Engineering.¬†
  • Solid understanding of VLSI system & sub-micron CMOS circuits design
  • Physical Design EDA tools knowledge (Cadence, Synopsys and Ansys)
  • Strong Scripting skills in (Perl, Tcl, shell, etc)
  • Good communication skills, self-motivated team player working in collaborative work environment.